---
--- Continue row requester
---

library ieee;
use ieee.std_logic_1164.all;

entity fc_rowrequester is
	port (
		rst : in std_logic;
		clk : in std_logic;
		row_req_in : in std_logic_vector(22 downto 0);
		row_req_out : out std_logic_vector(22 downto 0)
	);
end entity fc_rowrequester;

architecture behavioural of fc_rowrequester is
	signal old_row_req : std_logic_vector(22 downto 0);
	signal timer : natural range 0 to 2000;
begin
	process(clk, rst)
	begin
		if rst = '1' then
			row_req_out <= (others => '0');
			old_row_req <= (others => '0');
		elsif rising_edge(clk) then
			row_req_out <= (others => '0');
			
			if (row_req_in /= old_row_req) and (row_req_in /= "00000000000000000000000") then
				old_row_req <= row_req_in;
				row_req_out <= row_req_in;
				timer <= 0;
			else
				if timer >= 2000 then
					row_req_out <= old_row_req;
					timer <= 0;
				else
					timer <= timer + 1;
				end if;
			end if;
		end if;
	end process;
end architecture;
					
		
